An electrical optimizer that considers physical layout

• Published in: Annual ACM IEEE Design Automation Conference: Proceedings of the 25th ACM/IEEE conference on Design automation; 12-15 June 1988 pp. 453 - 459
• Main Authors: Obermeier, Fred W, Katz, Randy H
• Format: Conference Proceeding
• Language: English
• Published: 01.06.1988
• ISBN: 0818688645; 9780818688645
• DOI: 10.1145/37888.37905

Electrical performance and area improvement are important parts of the overall VLSI design task. Given designer specified constraints on area, delay, and power, EPOXY will size a circuit's transistors and will attempt small circuit changes to help meet the constraints. In addition, the system provides a flexible framework within which to evaluate the effects of different area and electrical models, as well as different optimization algorithms. Since the sum of transistor area is a better measure of dynamic power than cell area, a more accurate area model is presented. Optimization of a CMOS eight-stage inverter chain illustrates this difference; a typical minimum power implementation is 32.3% larger than the one for minimum area. The combination of a TILOS-style heuristic and augmented Lagrangian optimization algorithm yields quality results rapidly. EPOXY'S circuit analysis is from 5 to 56 times faster than Crystal.