220 mm super(2) 4 and 8 bank 256 Mb SDRAM with single-sided stitched WL architecture

A 220 mm super(2) 256 Mb SDRAM that uses single-sided stitched-wordline architecture, a shared row decoder with asymmetric block activation, an intra-unit address increment pipeline scheme, single-ended read-write drive, and selectable row domain and divided column redundancy is presented. This chip...

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Published inDigest of technical papers - IEEE International Solid-State Circuits Conference
Main Authors Kirihata, T, Gall, M, Hosokawa, K, Dortu, J-M, Wong, H, Pfefferl, K-P, Ji, B, Weinfurtner, O, DeBrosse, J, Terletzki, H, Selz, M, Ellis, W, Wordeman, M, Kiehl, O
Format Journal Article
LanguageEnglish
Published 01.01.1998
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Summary:A 220 mm super(2) 256 Mb SDRAM that uses single-sided stitched-wordline architecture, a shared row decoder with asymmetric block activation, an intra-unit address increment pipeline scheme, single-ended read-write drive, and selectable row domain and divided column redundancy is presented. This chip contains 8 32 Mb double units. Either the left or the right 16 Mb unit in each selected 32 Mb double unit is further decoded. A 4 bank SDRAM is realized by assigning 13 row addresses with 2 bank addresses. Two sets of 16 DQs and 16 read-write lines are arranged on the left and right chip halves.
Bibliography:SourceType-Scholarly Journals-2
ObjectType-Conference Paper-1
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SourceType-Conference Papers & Proceedings-1
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ISSN:0193-6530