A 40mm super(2) 3V 50MHz 64Mb 4-level cell NOR-type flash memory

The 64Mb 4-level cell flash memory devices was studied using a triple-metal triple-well p-bulk 0.18 mu m complementary metal oxide semiconductor (CMOS). The flash memory used shallow trench isolation (STI) for denser memory array packing. The charge-pump voltage multipliers were used to generate the...

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Published inDigest of technical papers - IEEE International Solid-State Circuits Conference
Main Authors Campardo, G, Micheloni, R, Commodaro, S, Yero, E, Zammattio, M, Mognoni, S, Sacco, A, Picca, M, Manstretta, A, Scotti, M, Motta, I, Golla, C, Pierin, A, Ohba, A, Futatsuya, T
Format Journal Article
LanguageEnglish
Published 01.01.2000
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Summary:The 64Mb 4-level cell flash memory devices was studied using a triple-metal triple-well p-bulk 0.18 mu m complementary metal oxide semiconductor (CMOS). The flash memory used shallow trench isolation (STI) for denser memory array packing. The charge-pump voltage multipliers were used to generate the high voltages for memory operations. Staircase-gate voltage programming and verify techniques were used to achieve sufficiently tight threshold voltage distributions.
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ISSN:0193-6530