InAs N-MOSFETs with record performance of I sub(on) = 600 mu A/ mu m at I sub(off) = 100 nA/ mu m (V sub(d) = 0.5 V)

• Published in: Technical digest - International Electron Devices Meeting pp. 16.1.1 - 16.1.4
• Main Authors: Chang, S W, Li, Xu, Oxland, R, Wang, S W, Wang, CH, Contreras-Guerrero, R, Bhuwalka, K K, Doornbos, G, Vasen, T, Holland, M C, Vellianitis, G, van Dal, MJH, Duriez, B, Edirisooriya, M, Rojas-Ramirez, J S, Ramvall, P, Thoms, S, Peralagu, U, Hsieh, CH, Chang, Y S, Yin, K M, Lind, E, Wernersson, L-E, Droopad, R, Thayne, I, Passlack, M, Diaz, CH
• Format: Journal Article
• Language: English
• Published: 01.12.2013
• Subjects: Channels; Devices; Dielectrics; High electron mobility transistors; Indium arsenides; MOSFETs; Simulation; State of the art
• ISSN: 2156-017X
• DOI: 10.1109/IEDM.2013.6724639

Record setting III-V MOSFETs are reported. For the first time performance better than state-of-the-art HEMTs is demonstrated. For a MOSFET with 10 nm unstrained InAs surface channel and L sub(g) = 130 nm operating at 0.5 V, on-current as high as I sub(on) = 601 mu A/ mu m (at fixed I sub(off) = 100 nA/ mu m) is achieved. This record performance is enabled by g sub(m, ext) = 2.72 mS/ mu m and S = 85 mV/dec, DIBL = 40 mV/V, resulting from breakthroughs in epitaxy and III-V/dielectric interface engineering. Measured mobility is 7100 cm super(2)/V.s at n sub(s) = 6.710 super(12) cm super(-2). Device simulations further elucidate the performance potential of III-V N-MOSFETs.