Interplay of plasma etch, strip and wet clean in patterning La sub(2)O sub(3)/HfO sub(2)-containing high- Kappa /metal gate stacks

The removal process of the La sub(2)O sub(3)/HfO sub(2) dielectric and of the residues after metal gate etch are discussed. The challenges are presented and related to the specific physico-chemical properties of La-containing compounds. Solutions based on optimization of plasma etch, strip and wet c...

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Published inMicroelectronic engineering Vol. 88; no. 1; pp. 21 - 27
Main Authors Vos, Ingrid, Hellin, David, Boullart, Werner, Vertommen, Johan
Format Journal Article
LanguageEnglish
Published 01.01.2011
Subjects
Cleaning
Etching (metallography)
Gates
Hafnium oxide
Optimization
Patterning
Residues
Strip
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Summary:The removal process of the La sub(2)O sub(3)/HfO sub(2) dielectric and of the residues after metal gate etch are discussed. The challenges are presented and related to the specific physico-chemical properties of La-containing compounds. Solutions based on optimization of plasma etch, strip and wet clean are demonstrated for both an integrated and delayed etch-clean process. Both processes meet the stringent requirements of complete removal of the high- Kappa layers and metal-containing sidewall residues without inducing silicon recess or undercut.
Bibliography:ObjectType-Article-1
SourceType-Scholarly Journals-1
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ISSN:0167-9317
DOI:10.1016/j.mee.2010.08.009