Linking EUV lithography line edge roughness and 16ANBnm NAND memory performance

• Published in: Microelectronic engineering Vol. 98; pp. 24 - 28
• Main Authors: Vaglio Pret, Alessandro, Poliakov, Pavel, Gronheid, Roel, Blomme, Pieter, Miranda Corbalan, Miguel, Dehaene, Wim, Verkest, Diederik, Van Houdt, Jan, Bianchi, Davide
• Format: Journal Article
• Language: English
• Published: 01.10.2012
• Subjects: Computer simulation; Density; Devices; Lithography; Monte Carlo methods; Resists; Roughness; Smoothing
• ISSN: 0167-9317
• DOI: 10.1016/j.mee.2012.04.013

Resist roughness is one of the effects of process uncertainties in extreme UV lithography. All the lithographic elements, such as source, mask, optical system, resist and metrology, contribute to line roughness. As a result, line edge roughness is still a challenge to be tackled for 22 and 16 nm transistor devices. In this paper, the impact of post-litho smoothing processes such as ion-beam implant and plasma etch treatment on state-of-the-art extreme UV lithography is reported. Top-down and cross section electron microscopy were used to evaluate low and high frequency components of line edge roughness by means of power spectral density analysis. To compute roughness impact on bit error rate performance of floating gate devices, line edge profiles were first rebuilt, and then injected into a Monte Carlo variability aware simulator for electrical evaluation of a 16 nm multi-level NAND Flash memory array. Electrical variability simulations based on actual experimental roughness profiles were executed to quantify the impact of line edge roughness on the device reliability. It was found that inter-transistor low frequency roughness impacts the memory performance with a failure factor 3-5 times higher compared to the same electrical model without considering any stochastic variation. Intra-transistor high frequency roughness showed only a marginal effect compared inter-transistor variations. Moreover, it was demonstrated that the bit error rate exponentially depend on resist line edge roughness. Finally, by combining both experimental analysis and electrical assessment, it was possible to quantify the contribution of post-litho smoothing processes on the error correction code performance for such memory devices.