On the SiO2-based gate-dielectric scaling limit for low-standby power applications in the context of a 0.13 [mu]m CMOS logic technology

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Bibliographic Details
Published inIEEE transactions on electron devices Vol. 49; no. 3; p. 442
Main Authors Lin, Yo-Sheng, Huang, Huan-Tsung, Wu, Chung-Cheng, Leung, Ying-Keung, Pan, Hsu-Yang, Chang, Tse-En, Chen, Wei-Ming, Liaw, Jung-Jih, Diaz, C.H
Format Journal Article
LanguageEnglish
Published New York The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 01.03.2002
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ISSN:0018-9383
1557-9646
DOI:10.1109/16.987115