TaN and [Formula Omitted] Sidewall Gate-Etch Damage Influence on Program, Erase, and Retention of Sub-50-nm TANOS nand Flash Memory Cells

• Published in: IEEE transactions on electron devices Vol. 58; no. 6; p. 1728
• Main Authors: Beug, M. Florian, Melde, Thomas, Paul, Jan, Knoefler, Roman
• Format: Journal Article
• Language: English
• Published: New York The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 01.06.2011
• Subjects: Semiconductors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2011.2121070

The sidewall gate-etch damage influence on the electrical behavior of 48-nm [Formula Omitted] (TANOS) nand charge-trapping memory cells is investigated in detail. This etch damage occurs at the sidewall of the high work-function TaN metal gate and high-[Formula Omitted] [Formula Omitted] blocking-oxide layers and adversely affects the electrical performance and the mechanical stability of small-ground-rule TANOS cells. Both issues could be solved for 48-nm TANOS cells by the introduction of a new integration scheme, which includes a removable encapsulation liner. This SiN liner protects the TaN sidewall from the etch damage during the aggressive [Formula Omitted] high- [Formula Omitted] etch process. The optimum of the 48-nm electrical cell performance was found for a 4-nm encapsulation liner thickness. In contrast to 48-nm TANOS cells, the encapsulation liner thickness does not affect the electrical performance of large 5-[Formula Omitted]-long-and-wide memory cells. The memory cell performance dependence on the TANOS liner thickness and memory cell size is explained by a damaged [Formula Omitted] region approximately 3-4 nm thick at the block oxide side wall. As a result, the reported etch damage exhibits a new scaling issue for TANOS memory cells around the 20-nm technology node when the total encapsulation liner thickness approaches half of the memory cell length.