Submicrometer Ultralow-Power TFT With 1.8 nm NAOS [Formula Omitted] CVD [Formula Omitted] Gate Stack Structure

• Published in: IEEE transactions on electron devices Vol. 58; no. 4; p. 1134
• Main Authors: Kubota, Yasushi, Matsumoto, Taketoshi, Imai, Shigeki, Yamada, Mikihiro, Tsuji, Hiroshi, Taniguchi, Kenji, Terakawa, Sumio, Kobayashi, Hikaru
• Format: Journal Article
• Language: English
• Published: New York The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 01.04.2011
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2011.2108657

We have fabricated submicrometer ultralow-power thin-film transistors (TFTs) with stack gate dielectric structure formed by the nitric acid oxidation of Si (NAOS) method. A 1.8 nm NAOS [Formula Omitted] layer effectively blocks the leakage current, and consequently, the thickness of a gate oxide layer deposited on the NAOS [Formula Omitted] layer can be made as thin as 20 nm. Because of the thin gate oxide layer, submicrometer TFTs with gate length in the range of [Formula Omitted]-[Formula Omitted] can be fabricated. The operation voltage of the TFTs can be set as low as 1.5 V because of the low threshold voltages (i.e., [Formula Omitted]0.6 V for P-ch TFT and 0.6 V for N-ch TFT). The drain current versus source-drain voltage curves possess an ideal feature with sufficiently high saturation currents even at 1.5 V operation voltage. The drain current versus gate voltage curves show a sharp current increase, and the subthreshold swing value is [Formula Omitted]80 mV/dec for both P-ch and N-ch TFTs. The on/off ratio is [Formula Omitted] for both P-ch and N-ch TFTs, and the channel mobility is [Formula Omitted] for P-ch TFT and [Formula Omitted] for N-ch TFT.