Guest Editorial Chip and Package-Scale Communication-Aware Architectures for General-Purpose, Domain-Specific, and Quantum Computing Systems

• Published in: IEEE journal on emerging and selected topics in circuits and systems Vol. 14; no. 3; p. 349
• Main Authors: Das, Abhijit, Palesi, Maurizio, Kim, John, Pande, Partha Pratim
• Format: Journal Article
• Language: English
• Published: Piscataway The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 01.01.2024
• Subjects: Innovations; Quantum computing
• ISSN: 2156-3357; 2156-3365
• DOI: 10.1109/JETCAS.2024.3445208

This Special Issue of IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) is devoted to advancing the field of chip and package-scale communications across diverse computing domains, bridging academic research and industrial innovation. As we enter a new golden age of computer architecture, marked by both challenges and opportunities, the anticipated end of Moore’s law necessitates reimagining the future of computing systems as we approach the physical limits of transistors. Three leading approaches to address these challenges include the chiplet paradigm, domain-specific customization, and quantum computing. However, these architectural and technological innovations have shifted the primary bottleneck from computation to communication. Consequently, on-chip and on-package communication now play a critical role in determining the performance, efficiency, and scalability of general-purpose, domain-specific, and quantum computing systems. Their ever-growing importance has garnered significant attention from both academia and industry.