A 0.2–3-GHz N-Path True Time Delay Circuit Achieving

• Published in: IEEE transactions on microwave theory and techniques Vol. 70; no. 6; p. 3224
• Main Authors: Zolkov, Erez, Cohen, Emanuel
• Format: Journal Article
• Language: English
• Published: New York The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 01.01.2022
• Subjects: Bandwidths; Broadband; Delay circuits; Power consumption; Time lag
• ISSN: 0018-9480; 1557-9670
• DOI: 10.1109/TMTT.2022.3162191

[Formula Omitted]-path true time delay (TTD) circuits are highly attractive due to their high delay-bandwidth product, wideband response, scalability, and small size. However, in its standalone form, it cannot provide wideband input and output matching. To overcome these issues, we present a modified circuit of the [Formula Omitted]-path TTD that includes an input low-noise amplifier (LNA) and an output buffer. The [Formula Omitted]-path TTD response and its nonideal properties are analyzed further. A design guide is suggested, and an alternative isolated sampling switch is proposed. We present a 65-nm CMOS dedicated implementation, where the fine-tuning of the TTD is achieved by introducing two synchronized external local oscillator (LO) signals, with a relative shift between them. The core chip size is [Formula Omitted] mm2, and its power consumption is 30 mW for all delay states. In our implementation, we achieve a delay range of 1 ns for bandwidth (BW) of 0.2–3 GHz with a gain standard deviation (STD) of less than 0.14 dB between delay states and a relative delay STD of less than 10 ps (1%) over frequency.