J SWof 5.5 MA/cm2 and RA of 5.2-Ω · μm2 STT-MRAM Technology for LLC Application

• Published in: IEEE transactions on electron devices Vol. 67; no. 9; p. 3618
• Main Authors: Sakhare, Sushil, Rao, Siddharth, Perumkunnil, Manu, Couet, Sebastien, Crotti, Davide, Simon Van Beek, Furnemont, Arnaud, Catthoor, Francky, Kar, Gouri Sankar
• Format: Journal Article
• Language: English
• Published: New York The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 01.01.2020
• Subjects: Access time; Circuits; CMOS; Computer simulation; Density; Diameters; Random access memory; Static random access memory; Technology transfer
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2020.3012123

Due to the complexity of device processing, the trade-off between yield and area has resulted in diminishing rate of scaling for the high-density static random access memory (SRAM) cell at advanced CMOS nodes. An introduction of extreme ultraviolet (EUV) and multipatterning has added additional cost to technology in order to realize 3-D device structure and ultrascaled metal routing. In this era, spin-transfer torque (STT)-MRAM technology can provide an alternative to high-density SRAM and for the last level cache (LLC) applications. In this article, we discuss the memory design and technology tradeoff to enable the STT-MRAM as a viable option. We have realized the technology over 300-mm wafer, measuring 1 million samples to build a SPICE model for circuit simulation. Occupying up to 83.3% of an area that of SRAM macro has been designed and simulated for the scaled 5-nm CMOS node. The simulated MRAM macro shows the best read and write access time of 3.1 and 6.2 ns, respectively. Magnetic tunneling junction (MTJ) pillar of 38-nm diameter is realized at 90-nm pitch, measuring resistance area (RA) of 5.2-[Formula Omitted], [Formula Omitted] of 5.5 MA/cm2 with improved [Formula Omitted]avg of 70, and breakdown voltage of 0.99 V. The energy comparison shows increasing gains versus SRAM for the increasing cache sizes crossing over at of 0.3 and 4 MB for the single-cycle read and write operations, respectively.