A WCET-aware cache coloring technique for reducing interference in real-time systems

The predictability of a system is the condition to give saferbound on worst case execution timeof real-time tasks which are running on it. Commercial off-the-shelf(COTS) processors are in-creasingly used in embedded systems and contain shared cache memory. This component hasa hard predictable behavi...

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Bibliographic Details
Published inarXiv.org
Main Authors Bouquillon, Fabien, Ballabriga, Clément, Lipari, Giuseppe, Smail Niar
Format Paper
LanguageEnglish
Published Ithaca Cornell University Library, arXiv.org 20.05.2019
Subjects
Coloring
Commercial off-the-shelf technology
Computer memory
Embedded systems
Preempting
Real time
Task scheduling
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Summary:The predictability of a system is the condition to give saferbound on worst case execution timeof real-time tasks which are running on it. Commercial off-the-shelf(COTS) processors are in-creasingly used in embedded systems and contain shared cache memory. This component hasa hard predictable behavior because its state depends of theexecution history of the systems.To increase predictability of COTS component we use cache coloring, a technique widely usedto partition cache memory. Our main contribution is a WCET aware heuristic which parti-tion task according to the needs of each task. Our experiments are made with CPLEX an ILPsolver with random tasks set generated running on preemptive system scheduled with earliestdeadline first(EDF).
ISSN:2331-8422