Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub-[Formula Omitted] A Sensing Resolution, and 17.5-nS Read Access Time

• Published in: IEEE journal of solid-state circuits Vol. 54; no. 4; p. 1029
• Main Authors: Yi-Chun, Shih, Chia-Fu, Lee, Yen-An, Chang, Po-Hao, Lee, Lin, Hon-Jarn, Yu-Lin, Chen, Ku-Feng, Lin, Ta-Ching Yeh, Hung-Chang, Yu, Chuang, Harry H L, Yu-Der Chih, Chang, Jonathan
• Format: Journal Article
• Language: English
• Published: New York The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 01.01.2019
• Subjects: Access time; Circuit design; CMOS; Sense amplifiers
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2018.2889106

A new MRAM reference and sensing circuit that can achieve <±1 [Formula Omitted] resolution and 17.5 nS read access from −40 °C to 125 °C is presented in this paper. A trimmable current-mode latch-type sense amplifier (CLSA) with hybrid-resistance-reference (HRR) and cell location compensation is proposed to resolve small read margin of MRAM. Silicon data measurement is presented to demonstrate a logic-process compatible, fully functional 16-Mb perpendicular MRAM in 40-nm CMOS process. Similar read circuit design concept can be applied to other technology nodes. Another test chip designed in 22 nm achieves wafer level average raw bit-error-rate (BER) of ~0.2 ppm and less than 2-ppm BER for 95th percentile chip.