A 12-Bit 31.1-[Formula Omitted]W 1-MS/s SAR ADC With On-Chip Input-Signal-Independent Calibration Achieving 100.4-dB SFDR Using 256-fF Sampling Capacitance

A 12-bit 31.1-[Formula Omitted] 1-MS/s successive approximation register analog-to-digital converter (ADC) with on-chip input-signal-independent calibration achieving 100.4-dB spurious-free dynamic range is presented. The proposed calibration overcomes the drawbacks of the conventional split-ADC cal...

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 54; no. 4; p. 937
Main Authors Shen, Junhua, Shikata, Akira, Liu, Anping, Chen, Baozhen, Chalifoux, Frederick
Format Journal Article
LanguageEnglish
Published New York The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 01.01.2019
Subjects
Analog to digital conversion
Analog to digital converters
Calibration
Capacitance
Capacitors
Circuit design
Dithering
Linearity
Sampling
Switching circuits
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Summary:A 12-bit 31.1-[Formula Omitted] 1-MS/s successive approximation register analog-to-digital converter (ADC) with on-chip input-signal-independent calibration achieving 100.4-dB spurious-free dynamic range is presented. The proposed calibration overcomes the drawbacks of the conventional split-ADC calibration while maintaining fast convergence. The calibration only needs one ADC and is input signal independent. Three techniques are proposed to help achieve this, including shuffling of mismatched MSB capacitors, MSB–LSB swapping, and partial MSB unit-capacitor dithering. In addition, partial bit trial and split-bottom switching circuit techniques are proposed. Silicon results fully validated the design and show 16-bit linearity with only 256-fF sampling capacitance.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2018.2883084