Maximum density of quantum information in a scalable CMOS implementation of the hybrid qubit architecture

Scalability from single qubit operations to multi-qubit circuits for quantum information processing requires architecture-specific implementations. Semiconductor hybrid qubit architecture is a suitable candidate to realize large scale quantum information processing, as it combines a universal set of...

Full description

Saved in:
Bibliographic Details
Published inarXiv.org
Main Authors Rotta, Davide, De Michielis, Marco, Ferraro, Elena, Fanciulli, Marco, Prati, Enrico
Format Paper
LanguageEnglish
Published Ithaca Cornell University Library, arXiv.org 05.06.2014
Subjects
CMOS
Coding
Data processing
Density
Error correction
Fault tolerance
Gates (circuits)
Information processing
Logic circuits
Metal oxides
Quantum computing
Quantum dots
Quantum phenomena
Quantum theory
Qubits (quantum computing)
Online AccessGet full text

Cover

More Information
Summary:Scalability from single qubit operations to multi-qubit circuits for quantum information processing requires architecture-specific implementations. Semiconductor hybrid qubit architecture is a suitable candidate to realize large scale quantum information processing, as it combines a universal set of logic gates with fast and all-electrical manipulation of qubits. We propose an implementation of hybrid qubits, based on Si Metal-Oxide-Semiconductor (MOS) quantum dots, compatible with the CMOS industrial technologic standards. We discuss the realization of multi-qubit circuits capable of fault-tolerant computation and quantum error correction, by evaluating the time and space resources needed for their implementation. As a result, the maximum density of quantum information is extracted from a circuit including 8 logical qubits encoded by the [[7,1,3]] Steane code. The corresponding surface density of logical qubits is 2.6 Mqubit/cm\(^2\).
ISSN:2331-8422