Parallel Programming Model for the Epiphany Many-Core Coprocessor Using Threaded MPI

The Adapteva Epiphany many-core architecture comprises a 2D tiled mesh Network-on-Chip (NoC) of low-power RISC cores with minimal uncore functionality. It offers high computational energy efficiency for both integer and floating point calculations as well as parallel scalability. Yet despite the int...

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Bibliographic Details
Published inarXiv.org
Main Authors Ross, James A, Richie, David A, Park, Song J, Shires, Dale R
Format Paper
LanguageEnglish
Published Ithaca Cornell University Library, arXiv.org 17.06.2015
Subjects
Algorithms
Architecture
Computing time
Coprocessors
Energy management
Finite element method
Floating point arithmetic
Matrices (mathematics)
Message passing
Microprocessors
Multiplication
Networks
Parallel programming
Particle interactions
Power management
Product development
System on chip
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Summary:The Adapteva Epiphany many-core architecture comprises a 2D tiled mesh Network-on-Chip (NoC) of low-power RISC cores with minimal uncore functionality. It offers high computational energy efficiency for both integer and floating point calculations as well as parallel scalability. Yet despite the interesting architectural features, a compelling programming model has not been presented to date. This paper demonstrates an efficient parallel programming model for the Epiphany architecture based on the Message Passing Interface (MPI) standard. Using MPI exploits the similarities between the Epiphany architecture and a conventional parallel distributed cluster of serial cores. Our approach enables MPI codes to execute on the RISC array processor with little modification and achieve high performance. We report benchmark results for the threaded MPI implementation of four algorithms (dense matrix-matrix multiplication, N-body particle interaction, a five-point 2D stencil update, and 2D FFT) and highlight the importance of fast inter-core communication for the architecture.
ISSN:2331-8422