A 481pJ/decision 3.4M decision/s Multifunctional Deep In-memory Inference Processor using Standard 6T SRAM Array

This paper describes a multi-functional deep in-memory processor for inference applications. Deep in-memory processing is achieved by embedding pitch-matched low-SNR analog processing into a standard 6T 16KB SRAM array in 65 nm CMOS. Four applications are demonstrated. The prototype achieves up to 5...

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Bibliographic Details
Published inarXiv.org
Main Authors Kang, Mingu, Gonugondla, Sujan, Patil, Ameya, Shanbhag, Naresh
Format Paper
LanguageEnglish
Published Ithaca Cornell University Library, arXiv.org 24.10.2016
Subjects
CMOS
Inference
Microprocessors
Static random access memory
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Summary:This paper describes a multi-functional deep in-memory processor for inference applications. Deep in-memory processing is achieved by embedding pitch-matched low-SNR analog processing into a standard 6T 16KB SRAM array in 65 nm CMOS. Four applications are demonstrated. The prototype achieves up to 5.6X (9.7X estimated for multi-bank scenario) energy savings with negligible (<1%) accuracy degradation in all four applications as compared to the conventional architecture.
ISSN:2331-8422