Performance enhancement of Ge-on-Insulator tunneling FETs with source junctions formed by low-energy BF^sub 2^ ion implantation

• Published in: Japanese Journal of Applied Physics Vol. 57; no. 4; p. 04FD15
• Main Authors: Katoh, Takumi, Matsumura, Ryo, Takaguchi, Ryotaro, Takenaka, Mitsuru, Takagi, Shinichi
• Format: Journal Article
• Language: English
• Published: Tokyo Japanese Journal of Applied Physics 01.04.2018
• Subjects: Atomic properties; Field effect transistors; Ion implantation; Leakage current; Performance enhancement; Semiconductor devices; Slopes; Substrates; Tunnel junctions
• ISSN: 0021-4922; 1347-4065

To clarify the process of formation of source regions of high-performance Ge n-channel tunneling field-effect transistors (TFETs), p+–n junctions formed by low-energy ion implantation (I/I) of BF2 atoms are characterized. Here, the formation of p+–n junctions with steep B profiles and low junction leakage is a key issue. The steepness of 5.7 nm/dec in profiles of B implanted into Ge is obtained for BF2 I/I at 3 keV with a dose of 4 x 1014 cm−2. Ge-on-insulator (GOI) n-TFETs with the source tunnel junctions formed by low-energy B and BF2 I/I are fabricated on GOI substrates and the device operation is confirmed. Although the performance at room temperature is significantly degraded by the source junction leakage current, an I on/I off ratio of 105 and the minimum sub-threshold swing (S.S.) of 130 mV/dec are obtained at 10 K. It is found that GOI n-TFETs with steeper B profiles formed by BF2 I/I have led to higher on current and a lower sub-threshold slope, demonstrating the effectiveness of steep B profiles in enhancing the GOI TFET performance.