Implementation of Crosstalk Avoidance and Low Power Coding Scheme for SoC

The paper proposes a coding scheme for avoiding crosstalk and reducing power consumption. System-on-Chip (S°C) buses are associated with delay, power and reliability problems. Capacitive crosstalk and high power consumption due to various capacitances are the major causes of this problem. Verilog si...

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Bibliographic Details
Published inIUP journal of telecommunications Vol. 10; no. 1; pp. 50 - 62
Main Authors Chakradhar, D, Obulesu, B
Format Journal Article
LanguageEnglish
Published Hyderabad IUP Publications 01.02.2018
Subjects
Advantages
Buses
Coding
Crosstalk
Error correction & detection
Power consumption
System on chip
Wire
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Summary:The paper proposes a coding scheme for avoiding crosstalk and reducing power consumption. System-on-Chip (S°C) buses are associated with delay, power and reliability problems. Capacitive crosstalk and high power consumption due to various capacitances are the major causes of this problem. Verilog simulation of encoder and decoder modules are designed to avoid these problems.
ISSN:0975-5551