A 0.008-mm2, 35-µW, 8.87-ps-resolution CMOS time-to-digital converter using dual-slope architecture

• Published in: International journal of circuit theory and applications Vol. 45; no. 4; p. 466
• Main Authors: Kim, Yeomyung, Shon, Doohyun, Kim, Tae Wook
• Format: Journal Article
• Language: English
• Published: Bognor Regis Wiley Subscription Services, Inc 01.04.2017
• ISSN: 0098-9886; 1097-007X
• DOI: 10.1002/cta.2272

Summary This paper presents a high resolution time-to-digital converter (TDC) for low-area applications. To achieve both high resolution and low circuit area, we propose a dual-slope voltage-domain TDC, which is composed of a time-to-voltage converter (TVC) and an analog-to-digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single-slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non-linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain-boosting current source is applied to overcome the low output impedance of the current source in the sub-100-nm CMOS process. The prototype TDC is implemented using a 65-nm CMOS process, and occupies only 0.008mm2. The measurement result shows a dynamic range with an 8-bit 8.86-ps resolution and an integrated non-linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.