A 0.9-μ² 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming
This paper introduces the first high-volume manufacturable (HVM) metal-fuse technology in a 14-nm trigate high-k metal-gate CMOS process. A high-density array featuring a 0.9-μ² bit cell with an efficient bit level redundancy scheme is presented. An array efficiency of over 53% is achieved through h...
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Published in | IEEE journal of solid-state circuits Vol. 52; no. 4; p. 933 |
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Main Authors | , , , , , |
Format | Journal Article |
Language | English |
Published |
New York
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
01.01.2017
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Subjects | |
Online Access | Get full text |
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Summary: | This paper introduces the first high-volume manufacturable (HVM) metal-fuse technology in a 14-nm trigate high-k metal-gate CMOS process. A high-density array featuring a 0.9-μ² bit cell with an efficient bit level redundancy scheme is presented. An array efficiency of over 53% is achieved through hierarchical bitline design by minimizing the impact of parasitic resistance on fuse programming through short local bitline and sharing sense amplifier through longer global bitline. A power gating-based scheme is adopted to reduce leakage current consumption and high-voltage exposure to minimize reliability concern. Program conditions can be optimized for HVM and in-field programming to achieve close to 100% unit level yield with the proposed redundancy scheme. |
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ISSN: | 0018-9200 1558-173X |
DOI: | 10.1109/JSSC.2016.2641955 |