Low Power and Area Efficient 2C Multiply- Accumulate Unit and Its Application to a DTMAC Unit

we propose a low power and area efficient two two-cycle multiply-accumulate (2C-MAC) architecture which supports 2's complement MAC) numbers, and includes accumulation guard bits and saturation circuitry. The first MAC pipeline stage contains only partial partial-product circuitry which is for...

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Bibliographic Details
Published inInternational journal of advanced research in computer science Vol. 3; no. 7
Main Authors V, Vimal Raj, S, Manikandababu C
Format Journal Article
LanguageEnglish
Published Udaipur International Journal of Advanced Research in Computer Science 01.11.2012
Subjects
Algorithms
Computer science
Critical path
Digital signal processors
Propagation
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Summary:we propose a low power and area efficient two two-cycle multiply-accumulate (2C-MAC) architecture which supports 2's complement MAC) numbers, and includes accumulation guard bits and saturation circuitry. The first MAC pipeline stage contains only partial partial-product circuitry which is for generating partial product. And the second stage consists of sign-extension block, saturation unit and all other functionality. Proposed architecture nd extension does not need any additional cycles to generate the final result. It efficiently produces the addition of the accumulated value and the product in each accumulated cycle. And extend the new architecture to create a double throughput MAC which can perform either multiply or multiply-accumulate operations.
ISSN:0976-5697