Memory Implementation using Multi Bit Flip-Flop

• Published in: I-Manager's Journal on Electronics Engineering Vol. 5; no. 2; p. 34
• Main Authors: Palagani Yellappa, Bharathkumar, Mareddi, Shaik, Shabana Azmi
• Format: Journal Article
• Language: English
• Published: Nagercoil iManager Publications 01.12.2014
• Subjects: Design engineering; Digital electronics; Memory expansion boards; Power supply
• ISSN: 2229-7286; 2249-0760

In the digital world memory elements play a vital role. In memory devices the most important factors are Area, Power and Speed. Increased Area and Power consumption of the memory device means reduced device reliability and lifetime. Flip-flops are the basic sequential components used for memory applications. D Flip-flop is one of the most commonly used Flip-flops and delay consumed by clocking is a major part of the whole design. In this paper, the authors analyze the design of Single-Bit Flip-Flop (SBFF i.e. 1-bit) and make a performance comparison over the Multi-Bit Flip-Flop (MBFF i.e. 2-bit, 4-bit, 8-bit, 16-bit and 32-bit). In this paper, the authors design SRAM and DRAM using both SBFF and MBFF in Xilinx Virtex-5 family (XC5VLX50). Designing the memory by using SBFF implies more power consumption. To get the maximum reduction in power and delay an algorithm has been proposed in which SBFFs are replaced with maximum possible MBFF without affecting the performance of the original circuit. These result in favor of Multi-Bit Flip-Flop as reduction of delay such as gate delay and net delay.