Linearisation of MOS resistors using capacitive gate voltage averaging
A compact implementation of a scheme to improve linearity of MOS resistors is introduced. It is based on capacitive gate voltage averaging in conjunction with the large resistive biasing elements implemented using MOS transistors operating in a subthreshold. The experimental results from a test chip...
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| Published in | Electronics letters Vol. 41; no. 9; p. 1 |
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| Main Authors | , , , |
| Format | Journal Article |
| Language | English |
| Published |
Stevenage
John Wiley & Sons, Inc
28.04.2005
|
| Online Access | Get full text |
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| Abstract | A compact implementation of a scheme to improve linearity of MOS resistors is introduced. It is based on capacitive gate voltage averaging in conjunction with the large resistive biasing elements implemented using MOS transistors operating in a subthreshold. The experimental results from a test chip in 0.5 μm CMOS technology are shown which verify the proposed technique. |
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| AbstractList | A compact implementation of a scheme to improve linearity of MOS resistors is introduced. It is based on capacitive gate voltage averaging in conjunction with the large resistive biasing elements implemented using MOS transistors operating in a subthreshold. The experimental results from a test chip in 0.5 μm CMOS technology are shown which verify the proposed technique. |
| Author | López-Martín, A Ramírez-Angulo, J Carvajal, R G Sawant, M S |
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| Copyright | Copyright The Institution of Engineering & Technology Apr 28, 2005 |
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| Title | Linearisation of MOS resistors using capacitive gate voltage averaging |
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