Linearisation of MOS resistors using capacitive gate voltage averaging

A compact implementation of a scheme to improve linearity of MOS resistors is introduced. It is based on capacitive gate voltage averaging in conjunction with the large resistive biasing elements implemented using MOS transistors operating in a subthreshold. The experimental results from a test chip...

Full description

Saved in:
Bibliographic Details
Published inElectronics letters Vol. 41; no. 9; p. 1
Main Authors Ramírez-Angulo, J, Sawant, M S, Carvajal, R G, López-Martín, A
Format Journal Article
LanguageEnglish
Published Stevenage John Wiley & Sons, Inc 28.04.2005
Online AccessGet full text

Cover

More Information
Summary:A compact implementation of a scheme to improve linearity of MOS resistors is introduced. It is based on capacitive gate voltage averaging in conjunction with the large resistive biasing elements implemented using MOS transistors operating in a subthreshold. The experimental results from a test chip in 0.5 μm CMOS technology are shown which verify the proposed technique.
ISSN:0013-5194
1350-911X