Low-Power DT [Formula Omitted] Modulators Using SC Passive Filters in 65 nm CMOS

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 61; no. 2; p. 358
• Main Authors: Yeknami, Ali Fazli, Qazi, Fahad, Alvandpour, Atila
• Format: Journal Article
• Language: English
• Published: New York The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 01.02.2014
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2013.2278346

A comparative design study of ultra-low-power discrete-time [Formula Omitted] modulators (DT [Formula Omitted]Ms) suited for medical implant devices is presented. Aiming to reduce the analog power consumption, the objective is to investigate the effectiveness of the switched-capacitor passive filter. Two design variants of 2nd-order [Formula Omitted]Ms are analyzed and compared to a power-optimized standard active modulator [Formula Omitted]. The first variant [Formula Omitted] employs an active filter in the 1st stage and a passive filter in the less critical 2nd stage. The second variant (OTA-less [Formula Omitted]) makes use of passive filters in both stages. For practical verification, all three modulators are implemented on a single chip in 65 nm CMOS technology. Designed for 500-Hz signal bandwidth, the [Formula Omitted] and [Formula Omitted] achieve 76 dB, 70 dB and 67 dB peak SNDR, while consuming 2.1 [Formula Omitted]W, 1.27 [Formula Omitted]W, and 0.92 [Formula Omitted]W, respectively, from a 0.9 V supply. Furthermore, the [Formula Omitted] can operate at a supply voltage reduced to 0.7 V, achieving a 65 dB SNDR at 430 nW power and 0.296 pJ/step.