High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using [Formula Omitted] Gate Stacks Fabricated by Plasma Postoxidation

• Published in: IEEE transactions on electron devices Vol. 60; no. 3; p. 927
• Main Authors: Zhang, Rui, Huang, Po-Chin, Lin, Ju-Chin, Taoka, Noriyuki, Takenaka, Mitsuru, Takagi, Shinichi
• Format: Journal Article
• Language: English
• Published: New York The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 01.03.2013
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2013.2238942

An ultrathin equivalent oxide thickness (EOT) [Formula Omitted] gate stack has been fabricated by combining the plasma postoxidation method with a 0.2-nm-thick [Formula Omitted] layer between [Formula Omitted] and Ge for suppressing [Formula Omitted] intermixing, resulting in a low-interface-state-density [Formula Omitted] [Formula Omitted] metal-oxide-semiconductor (MOS) interface. The EOT of these gate stacks has been scaled down to 0.7-0.8 nm with maintaining the [Formula Omitted] in [Formula Omitted] level. The p- and n-channel MOS field-effect transistors (MOSFETs) (p- and n-MOSFETs) using this gate stack have been fabricated on (100) Ge substrates and exhibit high hole and electron mobilities. It is found that the Ge p- and n-MOSFETs exhibit peak hole mobilities of 596 and 546 [Formula Omitted] and peak electron mobilities of 754 and 689 [Formula Omitted] at EOTs of 0.82 and 0.76 nm, respectively, which are the record-high reports so far for Ge MOSFETs in subnanometer EOT range because of the sufficiently passivated Ge MOS interfaces in present [Formula Omitted] gate stacks.