Gated Diode Investigation of Bias Temperature Instability in High- [Formula Omitted] FinFETs

• Published in: IEEE electron device letters Vol. 31; no. 7; p. 653
• Main Authors: Young, Chadwin D, Neugroschel, Arnost, Matthews, Kenneth, Smith, Casey, Heh, Dawei, Park, Hokyung, Hussein, Muhammad M, Taylor, William, Bersuker, Gennadi
• Format: Journal Article
• Language: English
• Published: New York The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 01.07.2010
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2010.2049635

Bias temperature instability (BTI) in FinFET transistors was investigated by charge-pumping (CP) and gated-diode measurements using [Formula Omitted] structures with the gate interface identical to that in SOI-FinFETs. The results show greatly improved sensitivity for gated diode measurements than for CP. The pre-stress interface trap density was found to be [Formula Omitted] for [Formula Omitted] nm-HfSiON/TiN/polySi-capped gate stacks, which is about one decade larger than in planar devices. The kinetics of [Formula Omitted] under negative bias stress conditions (NBTI) suggests [Formula Omitted] is generated by Si-H bond breaking. The mechanism for interface trap generation under positive bias stress conditions (PBTI) requires further investigation.