A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs
Saved in:
Published in | IEEE journal of solid-state circuits Vol. 35; no. 5; p. 713 |
---|---|
Main Authors | , , , , , , , , , , , , , , , , , , , , |
Format | Journal Article |
Language | English |
Published |
New York
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
01.05.2000
|
Online Access | Get full text |
Cover
Loading…
ISSN: | 0018-9200 1558-173X |
---|---|
DOI: | 10.1109/4.841498 |