Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories : Dependable Computing

• Published in: IEICE transactions on information and systems Vol. 96; no. 9; pp. 1914 - 1925
• Main Authors: IMAI, Masashi, YONEDA, Tomohiro
• Format: Journal Article
• Language: English
• Published: Oxford Oxford University Press 2013
• Subjects: Applied sciences; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Organization and planning of networks (techniques and equipments); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Systems, networks and services of telecommunications; Telecommunications; Telecommunications and information theory; Testing, measurement, noise and reliability; Interconnection network; fault diagnosis; network-on-chip; Processor; Redundancy; Network architecture; Mean time to failure; multiple processor system; System on a chip; Mismatching; pair and swap; Multiple system; Integrated circuit; Reconfigurable architectures; Reliability; Private sector; Fault diagnostic; Defect detection
• ISSN: 0916-8532; 1745-1361