A Medium-Grain Reconfigurable Architecture for DSP : VLSI Design, Benchmark Mapping, and Performance : CONFIGURABLE DESIGN-I: HIGH-LEVEL RECONFIGURATION

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Bibliographic Details
Published inIEEE transactions on very large scale integration (VLSI) systems Vol. 16; no. 1; pp. 14 - 23
Main Authors MYJAK, Mitchell J, DELGADO-FRIAS, José G
Format Journal Article
LanguageEnglish
Published Piscataway, NJ Institute of Electrical and Electronics Engineers 2008
Subjects
Applied sciences
Circuit properties
Design. Technologies. Operation analysis. Testing
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Performance evaluation
Interconnection network
Fast Fourier transformation
synthesis tools
Random access memory
Data transmission
Word length
Mapping
Flexibility
Implementation
Optimization
Multiplier
Digital signal processing (DSP)
floating-point arithmetic
Floating point
Reconfigurable architectures
Arithmetic circuit
VLSI circuit
Integrated circuit design
Field programmable gate array
Adder
Algorithm
Look up table
Software tool
medium-grain reconfigurable hardware
Integrated circuit
Digital signal processor
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ISSN:1063-8210
1557-9999