Impact of boron penetration from S/D-extension on gate-oxide reliability for 65-nm node CMOS and beyond

• Main Authors: YAMASHITA, T, OTA, K, NAKANISHI, K, NAKAOKA, H, YAMADA, T, NAKAMURA, M, MIYANAGA, I, KAJIYA, A, KUBOTA, M, OGURA, M, SHIGA, K, HAYASHI, T, UMEDA, H, ODA, H, EIMORI, T, INUISHI, M, OHJI, Y, ERIGUCHI, K
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ Business Center for Academic Societies; Tokyo IEEE
• Subjects: Applied sciences; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transistors; Thermal stress; Interfacial layer; Electric stress; Polycrystal; PMOS technology; Transistor gate; Doped materials; Nitriding; Optimization; Engraving; Gate oxide; Complementary MOS technology; Dielectric thin films; MOS transistor; Miniaturization; Low-power electronics; Reliability; NMOS technology; Electrical characteristic; Damaging
• ISBN: 0780382897; 9780780382893