칩 스택 패키지용 Sn 관통-실리콘-비아 형성공정 및 접속공정
Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be...
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| Published in | 대한금속·재료학회지, 48(6) pp. 557 - 564 |
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| Main Authors | , , |
| Format | Journal Article |
| Language | Korean |
| Published |
대한금속·재료학회
01.06.2010
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1738-8228 2288-8241 |
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| Summary: | Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing a much wider process window for the formation of Sn TSVs compared to the conventional Cu TSV process. Interlocking joints were processed by intercalation of Cu bumps into Sn vias to form interconnections between chips with Sn TSVs, and the mechanical integrity of the interlocking joints was evaluated with a die shear test. KCI Citation Count: 24 |
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| Bibliography: | G704-000085.2010.48.6.008 |
| ISSN: | 1738-8228 2288-8241 |