A Resolution-Configurable Charge-Domain Capacitance-to-Digital Converter

• Published in: IDEC Journal of Integrated Circuits and Systems, 11(2) pp. 35 - 39
• Main Authors: 김지수, 정인구, 박준은
• Format: Journal Article
• Language: English
• Published: 반도체설계교육센터 01.04.2025
• Subjects: 전기공학
• ISSN: 2384-2113
• DOI: 10.23075/jicas.2025.11.2.007

This paper presents a semi-digital capacitance-to-digital converter (CDC) with an extended input capacitance range of up to 1 nF, leveraging a configurable charge subtraction capacitor and a current mirror-based discharger to maintain high resolution. The proposed CDC employs a single-slope discharge mirror technique to achieve energy-efficient operation while eliminating complex analog circuits such as operational transconductance amplifiers (OTAs). The current mirror-based discharger with a charging flag mechanism enables precise charge sensing by dynamically controlling the charging and discharging processes, ensuring accurate capacitance. Additionally, this structure reduces circuit complexity while maintaining measurement accuracy and extending the supported input capacitance range. The configurable charge subtraction capacitor array further enhances flexibility, making the design suitable for various capacitive sensing applications, including pressure, humidity, and touch sensing. Post-layout simulations in a 180 nm CMOS process demonstrate a consistent conversion time across a wide capacitance range while maintaining low power consumption. Measurement results confirm a minimum resolution of 10 fF for a 1 nF input capacitance with single slope regulation. KCI Citation Count: 0