A Low-Power, Highly Linear Sub-GHz Receiver Front-End with a Voltage Follower-Based 4th-Order Channel Selection Filter

• Published in: IDEC Journal of Integrated Circuits and Systems, 10(4) pp. 25 - 30
• Main Authors: 김덕영, 박종원, 노예훈, 이겨레, 임동구
• Format: Journal Article
• Language: English
• Published: 반도체설계교육센터 01.10.2024
• Subjects: 전기공학
• ISSN: 2384-2113
• DOI: 10.23075/jicas.2024.10.4.005

A low-power, highly linear sub-GHz receiver front-end designed for LPWAN IoT applications is presented, featuring a voltage follower-based 4th-order channel selection filter. The receiver front-end comprises a wideband single-to-differential (S-to-D) low-noise amplifier (LNA), an in-phase/quadrature (I/Q) passive mixer, and the proposed advanced channel selection filter. The S-to-D LNA utilizes two cascaded inverters and a correction amplifier to achieve high gain, low noise, and high linearity while minimizing power consumption. The channel selection filter employs a novel design that combines the flipped voltage follower (FVF) and super source follower (SSF), enabling the implementation of a 4th-order filter without degrading the noise figure (NF). Implemented in 130-nm CMOS technology, the receiver achieves a conversion gain of approximately 30 dB, a double-sideband NF (NFDSB) of 3 dB at a cut-off frequency, and an output-referred third-order intercept point (OIP3) between +6.2 dBm and +7.7 dBm in the sub-GHz band, with a total power consumption of 8.9 mW from a 1.2 V supply A low-power, highly linear sub-GHz receiver front-end designed for LPWAN IoT applications is presented, featuring a voltage follower-based 4th-order channel selection filter. The receiver front-end comprises a wideband single-to-differential (S-to-D) low-noise amplifier (LNA), an in-phase/quadrature (I/Q) passive mixer, and the proposed advanced channel selection filter. The S-to-D LNA utilizes two cascaded inverters and a correction amplifier to achieve high gain, low noise, and high linearity while minimizing power consumption. The channel selection filter employs a novel design that combines the flipped voltage follower (FVF) and super source follower (SSF), enabling the implementation of a 4th-order filter without degrading the noise figure (NF). Implemented in 130-nm CMOS technology, the receiver achieves a conversion gain of approximately 30 dB, a double-sideband NF (NFDSB) of 3 dB at a cut-off frequency, and an output-referred third-order intercept point (OIP3) between +6.2 dBm and +7.7 dBm in the sub-GHz band, with a total power consumption of 8.9 mW from a 1.2 V supply. KCI Citation Count: 0