Compression-Friendly Low Power Test Application Based on Scan Slices Reusing
This paper presents a compression-friendly low power test scheme in EDT environment. The proposed approach exploits scan slices reusing to reduce the switching activity during shifting for test scheme based on linear decompressor. To avoid the impact on encoding efficiency from resulting control dat...
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Published in | Journal of semiconductor technology and science Vol. 16; no. 4; pp. 463 - 469 |
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Main Authors | , , , , |
Format | Journal Article |
Language | Korean |
Published |
2016
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Subjects | |
Online Access | Get full text |
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Summary: | This paper presents a compression-friendly low power test scheme in EDT environment. The proposed approach exploits scan slices reusing to reduce the switching activity during shifting for test scheme based on linear decompressor. To avoid the impact on encoding efficiency from resulting control data, a counter is utilized to generate control signals. Experimental results obtained for some larger ISCAS'89 and ITC'99 benchmark circuits illustrate that the proposed test application scheme can improve significantly the encoding efficiency of linear decompressor. |
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Bibliography: | KISTI1.1003/JNL.JAKO201625654348287 |
ISSN: | 1598-1657 |