An In-Band Noise Filtering 32-tap FIR-Embedded ΔΣ Digital Fractional-N PLL

• Published in: Journal of semiconductor technology and science Vol. 15; no. 3; pp. 342 - 348
• Main Authors: Lee, Jong Mi, Jee, Dong-Woo, Kim, Byungsub, Park, Hong-June, Sim, Jae-Yoon
• Format: Journal Article
• Language: Korean
• Published: 2015
• Subjects: phase rotator; fractional-N PLL; TDC; FIR filtering; frequency synthesizer; phase noise; {{\Delta}{\Sigma}}$ modulator
• ISSN: 1598-1657

This paper presents a 1.9-GHz digital ${{\Delta}{\Sigma}}$ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in $0.11-{\mu}m$ CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.