Decrease of Parasitic Capacitance for Improvement of RF Performance of Multi-finger MOSFETs in 90-nm CMOS Technology

In this paper, the RF characteristics of multi-finger MOSFETs were improved by decreasing the parasitic capacitance in spite of increased gate resistance in a 90-nm CMOS technology. Two types of device structures were designed to compare the parasitic capacitance in the gate-to-source ($C_{gs}$) and...

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Bibliographic Details
Published inJournal of semiconductor technology and science Vol. 15; no. 2; pp. 312 - 317
Main Authors Jang, Seong-Yong, Kwon, Sung-Kyu, Shin, Jong-Kwan, Yu, Jae-Nam, Oh, Sun-Ho, Jeong, Jin-Woong, Song, Hyeong-Sub, Kim, Choul-Young, Lee, Ga-Won, Lee, Hi-Deok
Format Journal Article
LanguageKorean
Published 2015
Subjects
layout
RF performance
cut-off frequency ( $f_T$)
Multi-finger MOSFET
parasitic capacitance
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Summary:In this paper, the RF characteristics of multi-finger MOSFETs were improved by decreasing the parasitic capacitance in spite of increased gate resistance in a 90-nm CMOS technology. Two types of device structures were designed to compare the parasitic capacitance in the gate-to-source ($C_{gs}$) and gate-to-drain ($C_{gd}$) configurations. The radio frequency (RF) performance of multi-finger MOSFETs, such as cut-off frequency ($f_T$) and maximum-oscillation frequency ($f_{max}$) improved by approximately 10% by reducing the parasitic capacitance about 8.2% while maintaining the DC performance.
Bibliography:KISTI1.1003/JNL.JAKO201514039404578
ISSN:1598-1657