A 1-V 1.6-GS/s 5.58-ENOB CMOS Flash ADC using Time-Domain Comparator

A 1-V 1.6-GS/s 5.58-ENOB flash ADC with a high-speed time-domain comparator is proposed. The proposed time-domain comparator, which consumes low power, improves the comparison capability in high-speed operations and results in the removal of preamplifiers from the first-stage of the flash ADC. The t...

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Bibliographic Details
Published inJournal of semiconductor technology and science Vol. 15; no. 6; pp. 695 - 702
Main Authors Lee, Han-Yeol, Jeong, Dong-Gil, Hwang, Yu-Jeong, Lee, Hyun-Bae, Jang, Young-Chan
Format Journal Article
LanguageKorean
Published 2015
Subjects
time interpolation
Flash ADC
low power
high-speed time-domain comparator
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Summary:A 1-V 1.6-GS/s 5.58-ENOB flash ADC with a high-speed time-domain comparator is proposed. The proposed time-domain comparator, which consumes low power, improves the comparison capability in high-speed operations and results in the removal of preamplifiers from the first-stage of the flash ADC. The time interpolation with two factors, implemented using the proposed time-domain comparator array and SR latch array, reduces the area and power consumption. The proposed flash ADC has been implemented using a 65-nm 1-poly 8-metal CMOS process with a 1-V supply voltage. The measured DNL and INL are 0.28 and 0.41 LSB, respectively. The SNDR is measured to be 35.37 dB at the Nyquist frequency. The FoM and chip area of the flash ADC are 0.38 pJ/c-s and $620{\times}340{\mu}m^2$, respectively.
Bibliography:KISTI1.1003/JNL.JAKO201502151147932
ISSN:1598-1657