A Low-Jitter DLL-Based Clock Generator with Two Negative Feedback Loops

• Published in: Journal of semiconductor technology and science Vol. 14; no. 4; pp. 457 - 462
• Main Authors: Choi, Young-Shig, Park, Jong-Yoon
• Format: Journal Article
• Language: Korean
• Published: 2014
• Subjects: delay locked loop; clock generator; delay-time variance voltage converter
• ISSN: 1598-1657

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.