Optimization of a Systolic Array BCH encoder with Tree-Type Structure

BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel e...

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Bibliographic Details
Published inInternational JOURNAL OF CONTENTS Vol. 9; no. 1; pp. 33 - 37
Main Authors Lim, Duk-Gyu, Shakya, Sharad, Lee, Je-Hoon
Format Journal Article
LanguageKorean
Published 2013
Subjects
tree-type systolic arrays
BCH code
encoder
parallel processing
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Summary:BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.
Bibliography:KISTI1.1003/JNL.JAKO201310837320482
ISSN:1738-6764
2093-7504