Design of Vector Register Architecture in DSP Processor for Efficient Multimedia Processing

In this paper, we present an efficient instruction set architecture using vector register file hardware to accelerate operation of general matrix-vector operations in DSP microprocessor. The technique enables in-situ row-access as well as column access to the register files. It can reduce the number...

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Bibliographic Details
Published inJournal of semiconductor technology and science Vol. 7; no. 4; pp. 229 - 234
Main Authors Wu, Chou-Pin, Wu, Jen-Ming
Format Journal Article
LanguageKorean
Published 2007
Subjects
264
Register File
instruction set architecture
H
DSP microprocessor
video signal processing
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Summary:In this paper, we present an efficient instruction set architecture using vector register file hardware to accelerate operation of general matrix-vector operations in DSP microprocessor. The technique enables in-situ row-access as well as column access to the register files. It can reduce the number of memory access significantly. The technique is especially useful for block-based video signal processing kernels such as FFT/IFFT, DCT/IDCT, and two-dimensional filtering. We have applied the new instruction set architecture to in-loop deblocking filter processing in H.264 decoder. Performance comparisons show that the required load/store operations for the in-loop deblocking filter can be reduced about 42%. The architecture would improve the processing speed, and code density in DSP microprocessor especially for video signal processing substantially.
Bibliography:KISTI1.1003/JNL.JAKO200709905808897
ISSN:1598-1657