리드-온-칩 패키지 기술로 조립된 반도체 디바이스에서 온도변화에 의해 발생되는 Si 3 N 4 손상

This article shows how fractures in the Si 3 N 4 layer, which comprises the top layer of semiconductor devices encapsulated utilizing a lead-on-chip (LOC) packaging technique, are influenced by changes in the lead-frame materials and thermal-cycling test conditions. Using thermal-cycling tests, it w...

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Bibliographic Details
Published in대한금속재료학회지 Vol. 61; no. 2; pp. 76 - 83
Main Authors 이성민, Seong-min Lee, 김연욱, Yeon-wook Kim
Format Journal Article
LanguageKorean
Published 대한금속재료학회 05.02.2023
Subjects
chip
fracture
reliability
semiconductor
stress
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Summary:This article shows how fractures in the Si 3 N 4 layer, which comprises the top layer of semiconductor devices encapsulated utilizing a lead-on-chip (LOC) packaging technique, are influenced by changes in the lead-frame materials and thermal-cycling test conditions. Using thermal-cycling tests, it was found that fractures in the Si 3 N 4 layer are the most sensitive to changes in the lead-frame materials at the early stage of thermal-cycling, between -65 ℃ and 150 ℃. Through SEM examinations and stress simulations, this work shows that adopting a copper lead-frame with a CTE-value similar to that of a package body effectively prevents filler-driven Si 3 N 4 damage, providing semiconductor devices with better reliability margins during thermal-cycling. (Received 14 July, 2022; Accepted 14 November, 2022)
Bibliography:The Korean Institute of Metals and Materials
ISSN:1738-8228