Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars Project supported by the National Natural Science Foundation of China (Grant Nos. 61704084 and 61874059)

• Published in: Chinese physics B Vol. 29; no. 3
• Main Authors: Yao, Jia-Fei, Guo, Yu-Feng, Zhang, Zhen-Yu, Yang, Ke-Meng, Zhang, Mao-Lin, Xia, Tian
• Format: Journal Article
• Language: English
• Published: Chinese Physical Society and IOP Publishing Ltd 01.02.2020
• Subjects: breakdown voltage; dielectric; high; step doped silicon pillar
• ISSN: 1674-1056
• DOI: 10.1088/1674-1056/ab6960

This paper presents a new silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor transistor (LDMOST) device with alternated high-k dielectric and step doped silicon pillars (HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage (BV) and specific on-resistance (Ron, sp) are obtained. The results indicate that the HKSD device has a higher BV and lower Ron, sp compared to the SD device and HK device.