Novel Topological Layout for ESD protection for high-speed I/O applications

Three diodes with novel topological layouts were researched and fabricated on the 22-nm CMOS process, by using TCAD tools and TLP test system. The interdigital diode without metal contacts can effectively reduce the turn-on resistance and the interdigital diode with metal contacts can significantly...

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Bibliographic Details
Published in2022 International EOS/ESD Symposium on Design and System (IEDS) pp. 1 - 4
Main Authors Ma, Qinling, Liang, Hailian
Format Conference Proceeding
LanguageEnglish
Published EOS/ESD Association, Inc 09.11.2022
Subjects
CMOS process
Electrostatic discharges
Layout
Metals
Performance evaluation
Resistance
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Summary:Three diodes with novel topological layouts were researched and fabricated on the 22-nm CMOS process, by using TCAD tools and TLP test system. The interdigital diode without metal contacts can effectively reduce the turn-on resistance and the interdigital diode with metal contacts can significantly improve the turn-on speed.