The role of test structures for yield enhancement and yield ramp-up: an example of adoptive yield enhancement (AYE): n/sup +//p-well junction leakage enhanced the abnormal leakage current of NMOS's parasitic NPN-BJT

The yield loss of an 0.25 /spl mu/m SRAM caused by the n/sup +//p-well junction leakage was characterized and categorized in two areas by physical location: one is located at the gate/drain region, the other is at the corner of shallow trench isolation. For timely and efficient solving and monitorin...

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Bibliographic Details
Published inProceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) pp. 261 - 264
Main Authors Doong, K.Y.Y., Binson Shen, Sunnys Hsieh, Sheng-che Lin, Hsu, C.C.-H.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2000
Subjects
Fabrication
Integrated circuit yield
Logic
Monitoring
MOS devices
Process control
Random access memory
Semiconductor device manufacture
Testing
Thermal stresses
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Summary:The yield loss of an 0.25 /spl mu/m SRAM caused by the n/sup +//p-well junction leakage was characterized and categorized in two areas by physical location: one is located at the gate/drain region, the other is at the corner of shallow trench isolation. For timely and efficient solving and monitoring of the fabrication line, two sets of test structures and corresponding measurement methods were designed for process monitoring and yield screening. Finally, based on the yield learning, we propose a test-structure-based process control and yield monitoring, called Adoptive Yield Enhancement (AYE).
ISBN:0780373928
9780780373921
ISSN:1523-553X
DOI:10.1109/ISSM.2000.993663