Cellular supercomputing with system-on-a-chip

System-on-a-chip technology allows a level of integration that can be leveraged to develop inexpensive high-performance, low-power computing nodes. When used in aggregate, this approach promises to challenge conventional supercomputer architectures in the high-performance computing arena. Systems un...

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Published in2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Vol. 1; pp. 196 - 197 vol.1
Main Authors Almasi, G., Almasi, G.S., Beece, D., Bellofatto, R., Bhanot, G., Bickford, R., Blumrich, M., Bright, A.A., Brunheroto, J., Cascaval, C., Castanos, J., Ceze, L., Coteus, P., Chatterjee, S., Chen, D., Chiu, G., Cipolla, T.M., Crumley, P., Deutsch, A., Dombrowa, M.B., Donath, W., Eleftheriou, M., Fitch, B., Gagliano, J., Gara, A., Germain, R., Giampapa, M.E., Gupta, M., Gustavson, F., Hall, S., Haring, R.A., Heidel, D., Heidelberger, P., Herger, L.M., Hoenicke, D., Jackson, R.D., Jamal-Eddine, T., Kopcsay, G.V., Lanzetta, A.P., Lieber, D., Lu, M., Mendell, M., Mok, L., Moreira, J., Nathanson, B.J., Newton, M., Ohmacht, M., Rand, R., Regan, R., Sahoo, R., Sanomiya, A., Schenfeld, E., Singh, S., Song, P., Steinmacher-Burow, B.D., Strauss, K., Swetz, R., Takken, T., Vranas, P., Ward, T.J.C., Brown, J., Liebsch, T., Schram, A., Ulsh, G.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2002
Subjects
Application specific integrated circuits
Bandwidth
Computer architecture
Delay
Ethernet networks
Network servers
Routing
Supercomputers
System-on-a-chip
Throughput
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Abstract System-on-a-chip technology allows a level of integration that can be leveraged to develop inexpensive high-performance, low-power computing nodes. When used in aggregate, this approach promises to challenge conventional supercomputer architectures in the high-performance computing arena. Systems under consideration reach into the hundreds of thousand nodes per machine. Architecture for these systems are described.
AbstractList System-on-a-chip technology allows a level of integration that can be leveraged to develop inexpensive high-performance, low-power computing nodes. When used in aggregate, this approach promises to challenge conventional supercomputer architectures in the high-performance computing arena. Systems under consideration reach into the hundreds of thousand nodes per machine. Architecture for these systems are described.
Author Chiu, G.
Gagliano, J.
Steinmacher-Burow, B.D.
Bellofatto, R.
Gara, A.
Lieber, D.
Nathanson, B.J.
Sahoo, R.
Moreira, J.
Herger, L.M.
Ceze, L.
Fitch, B.
Vranas, P.
Mok, L.
Bickford, R.
Heidelberger, P.
Kopcsay, G.V.
Newton, M.
Ward, T.J.C.
Deutsch, A.
Lu, M.
Mendell, M.
Cipolla, T.M.
Bhanot, G.
Heidel, D.
Germain, R.
Cascaval, C.
Giampapa, M.E.
Blumrich, M.
Regan, R.
Chen, D.
Takken, T.
Singh, S.
Strauss, K.
Crumley, P.
Dombrowa, M.B.
Beece, D.
Schram, A.
Almasi, G.
Song, P.
Liebsch, T.
Donath, W.
Eleftheriou, M.
Brunheroto, J.
Swetz, R.
Lanzetta, A.P.
Brown, J.
Ohmacht, M.
Haring, R.A.
Chatterjee, S.
Bright, A.A.
Hall, S.
Castanos, J.
Rand, R.
Almasi, G.S.
Jackson, R.D.
Schenfeld, E.
Gustavson, F.
Ulsh, G.
Sanomiya, A.
Hoenicke, D.
Coteus, P.
Gupta, M.
Jamal-Eddine, T.
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StartPage 196
SubjectTerms Application specific integrated circuits
Bandwidth
Computer architecture
Delay
Ethernet networks
Network servers
Routing
Supercomputers
System-on-a-chip
Throughput
Title Cellular supercomputing with system-on-a-chip
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