Cellular supercomputing with system-on-a-chip

• Published in: 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Vol. 1; pp. 196 - 197 vol.1
• Main Authors: Almasi, G., Almasi, G.S., Beece, D., Bellofatto, R., Bhanot, G., Bickford, R., Blumrich, M., Bright, A.A., Brunheroto, J., Cascaval, C., Castanos, J., Ceze, L., Coteus, P., Chatterjee, S., Chen, D., Chiu, G., Cipolla, T.M., Crumley, P., Deutsch, A., Dombrowa, M.B., Donath, W., Eleftheriou, M., Fitch, B., Gagliano, J., Gara, A., Germain, R., Giampapa, M.E., Gupta, M., Gustavson, F., Hall, S., Haring, R.A., Heidel, D., Heidelberger, P., Herger, L.M., Hoenicke, D., Jackson, R.D., Jamal-Eddine, T., Kopcsay, G.V., Lanzetta, A.P., Lieber, D., Lu, M., Mendell, M., Mok, L., Moreira, J., Nathanson, B.J., Newton, M., Ohmacht, M., Rand, R., Regan, R., Sahoo, R., Sanomiya, A., Schenfeld, E., Singh, S., Song, P., Steinmacher-Burow, B.D., Strauss, K., Swetz, R., Takken, T., Vranas, P., Ward, T.J.C., Brown, J., Liebsch, T., Schram, A., Ulsh, G.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2002
• Subjects: Application specific integrated circuits; Bandwidth; Computer architecture; Delay; Ethernet networks; Network servers; Routing; Supercomputers; System-on-a-chip; Throughput
• ISBN: 9780780373358; 0780373359
• DOI: 10.1109/ISSCC.2002.993003

System-on-a-chip technology allows a level of integration that can be leveraged to develop inexpensive high-performance, low-power computing nodes. When used in aggregate, this approach promises to challenge conventional supercomputer architectures in the high-performance computing arena. Systems under consideration reach into the hundreds of thousand nodes per machine. Architecture for these systems are described.