Design of a low-cost integrated 0.25 /spl mu/m CMOS Bluetooth SOC in 16.5 mm/sup 2/ silicon area

A complete 0.25 /spl mu/m CMOS SOC Bluetooth solution adopts a two-die in a single MCM chip packaging approach with minimum product cost as the most important design goal while maintaining competitive power consumption and RF performance.

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Bibliographic Details
Published in2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Vol. 1; pp. 90 - 449 vol.1
Main Authors Cheah, J., Ee-Hong Kwek, Eng Chuan Low, Chee Kwang Quek, Yong, C., Enright, R., Hirbawi, J., Lee, A., Hongyu Xie, Longyin Wei, Le Luong, Jianping Pan, Shih-Tsung Yang, Lau, W.F.A., Wai-Lim Ngai
Format Conference Proceeding
LanguageEnglish
Published IEEE 2002
Subjects
Band pass filters
Bluetooth
Calibration
CMOS technology
Costs
Digital filters
Frequency synthesizers
Linearity
Silicon
Voltage-controlled oscillators
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Summary:A complete 0.25 /spl mu/m CMOS SOC Bluetooth solution adopts a two-die in a single MCM chip packaging approach with minimum product cost as the most important design goal while maintaining competitive power consumption and RF performance.
ISBN:9780780373358
0780373359
DOI:10.1109/ISSCC.2002.992953